The present invention relates to a technology of reproducing duty for clock signals so as to lapse into desirable duty by a logic circuit unit operated in synchronism with the clock signals, and to a technology effective for application to a semiconductor integrated circuit.
In a logic circuit comprising a sequence circuit and a combinational circuit, the sequence circuit is normally synchronized with a clock signal to allow a latch operation. In many applications for the logic circuit, the clock signal may preferably be set to a duty ratio of 50% (ratio of high level period to high level and low level periods). In a high-speed operation logic IC, for example, PLL or an oscillator circuit such as a frequency programmable circuit is provided thereinside and each clock is supplied therefrom. Using a differential type circuit as an oscillator circuit such as VCO/ICO or the like makes it possible to generate complementary clock signals whose phase difference/duty ratio are both 50%. However, a duty shift or deviation caused by the difference between a rising propagation delay time tpLH of each clock signal and a falling propagation delay time tpHL thereof is developed in combinational logic provided at a subsequent stage of the oscillator circuit, such as a logic level converter, a clock selection circuit lying inside a logic unit.
The duty shift exerts an influence on the operating speed of the logic circuit. Namely, firstly, the limit of speed-up of a high-speed operation logic circuit is generally determined according to the sum of a delay time for a path (so-called critical path) in which a value obtained by adding (add-subtract calculation) a delay time developed from a clock signal input terminal of a flip-flop to data input terminals of subsequent-stage combinational logic and a next-stage flip-flop via the output of data of the flip-flop, the time required to set up the input of data of the flip-flop on the next-stage side, and a clock skew reaches a maximum within the logic circuit, etc. This value corresponds to a minimum value (maximum value as an operating frequency) determined with respect to the cycle of a clock pulse.
Secondly in addition to the above, operable minimum values are respectively included in an xe2x80x9cHxe2x80x9d (high level)xe2x80x9d width and an xe2x80x9cLxe2x80x9d (low level) width of a clock input waveform of each flip-flop. When a duty ratio for clocks is shifted from 50%, a high-speed operation limit might be determined in advance in terms of a clock width. This value corresponds to a minimum value determined with respect to each of the xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d widths other than the cycle of the clock pulse.
The duty ratio for the clock signals is determined according to both the configuration of a clock generator and a shift between tpLH and tpHL in a logic circuit provided at a stage subsequent to the clock generator.
After the invention of the present application has been completed by the present inventors, the present inventors have recognized the presence of first through third Laid-Open Publications. Japanese Patent Application Laid-Open No. Hei 7(1995)-30380 corresponding to the first Laid-Open Publication describes a latch technology of avoiding mistransmission of data between a master latch and a slave latch controlled by quarter-phase clock signals. Japanese Patent Application Laid-Open No. Hei 8(1996)-88545 corresponding to the second Laid-Open Publication describes a technology of transmitting pulse signals inputted to a buffer to a subsequent stage without disturbing a duty ratio. In the present disclosure, a duty ratio correction circuit comprises a series-connected circuit comprised of an edge detection circuit and a latch circuit. Japanese Patent Application Laid-Open No. Hei 7(1995)-21222 corresponding to the third Laid-Open Publication describes a voltage-controlled oscillator which forms an output having a duty ratio of 50%.
In third Laid-Open Publication in particular, differential frequency signals obtained by charging and discharging capacitive elements connected to differential analog input terminals are compared with each other and complementary analog signals are formed from the result of comparison. A latch circuit in which a pair of NAND gates is cross-connected, is used in serial two stages to thereby waveform-shape the complementary analog signals. A delay corresponding to a one-stage gate is developed between the waveform-shaped complementary clock signals. The waveform-shaped complementary clock signals are inputted to a two-input NAND gate. A clock having a narrow width equivalent to the gate delay developed between the input complementary clock signals is formed at the output of the two-input NAND gate. It is divided into two to thereby form clock signals having a duty ratio of 50%. The complementary outputs from the final stages of the serial two-stage latch circuits are fed back to complementarily activate switch circuits for charging and discharging the capacitive elements. In this configuration, the NAND-gate based latch circuits placed in the serial two stages aim to receive an analog output of a comparator and waveform-shape the analog output. Further, the waveform-shaped complementary outputs are fed back as complementary switch control signals for current switch circuits for charging and discharging the capacitive elements placed on the input side of the comparator. Therefore, the serial two-stage NAND latch circuits cannot be formed as components capable of being separated and grasped from the feedback system.
It is desirable that a duty ratio for clocks is close to 50% to take a high-speed operation margin or increase the maximum operating frequency. It is also desirable that when a duty ratio of 50% takes place at a given node, the difference between tpLH and tpHL is nonexistent at its subsequent stage where practicable. In other words, it has been revealed by the present inventors that it is desirable that the duty ratio of 50% can be achieved at a subsequent stage, i.e., at a clock input terminal of each flip-flop where practicable.
It is considered that in order to achieve the duty ratio of 50% to the utmost, for example, the oscillating frequency is set twice and divided into two by a logic circuit corresponding to a subsequent stage. However, in a high-speed operated application like a read channel LSI such as HDD (Hard Disc Drive), DVD (Digital Video Disc) or the like, the setting of the oscillating frequency to further twice is realistically difficult and undesirable in terms of power consumption and EMI (Electromagnetic Interference).
An object of the present invention is to provide a duty recovery or restoring technology capable of easily recovering a duty ratio for clock signals to a duty ratio of about 50% corresponding to a desirable state in the neighborhood of a sequence circuit even if the duty ratio for the clock signals breaks down at a logic circuit unit which inputs complementary clock signals and performs a logic operation, and a semiconductor integrated circuit to which the technology is applied.
Another object of the present invention is to provide a duty recovery technology capable of easily recovering a duty ratio for clock signals to a state of a desirable about 50% even if the duty ratio for the clock signals increases or decreases from about 50%, and a semiconductor integrated circuit to which the technology is applied.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] According to a first aspect of the present invention, serial two-stage static latches are used to correct duty. Namely, a semiconductor integrated circuit has an oscillator circuit (2) which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%, an output converter (3) which converts the complementary cycle signals outputted from the oscillator circuit to predetermined logic levels and outputs complementary clock signals having a phase difference of about half cycle therebetween, and a logic circuit unit (4) which inputs the complementary clock signals outputted from the output converter and performs a logic operation. The logic circuit unit includes a duty correction circuit (5) which corrects at least a duty shift between the complementary clock signals, which is developed at the output converter, and recovers the same to about 50%. The duty correction circuit has a first logic stage (44, 45) which inputs the complementary clock signals having passed the output converter, and a second logic stage (45, 55) which inputs the output of the first logic stage. The first logic stage performs a logic operation for correcting complementary clock signals having a duty ratio set to be shorter than a period for a first logical value at a duty ratio at which the period for the first logical value is about 50%, to a duty ratio of about 50%, and correcting the period for the first logical value so as to be shorter than the duty ratio of about 50% with respect to complementary clock signals having a duty ratio set to be longer than the period for the first logical value at the duty ratio at which the period for the first logical value is about 50%. The second logic stage inputs complementary clock signals outputted from the first logic stage, corrects complementary clock signals having a duty ratio set to be shorter than a period for a first logical value at a duty ratio at which the period for the first logical value is about 50%, to a duty ratio of about 50%, effects logical value inversion on complementary clock signals whose duty ratio is about 50%, and produces an output therefrom.
When NAND gates are used, as illustrated in FIG. 1, the first logic stage may be configured as a first NAND latch circuit (44) wherein the outputs of one NAND gates are respectively mutually feedback-connected to inputs of the other NAND gates, and complementary clock signals having the phase difference of about half cycle are supplied to the other inputs of the respective NAND gates. Further, the second logic stage may be configured as a second NAND latch circuit (45) wherein the outputs of one NAND gates are respectively mutually feedback-connected to inputs of the other NAND gates, and the outputs of the NAND gates of the first latch circuit are respectively supplied to the other inputs of the respective NAND gates. According to the configurations, as illustrated in FIG. 13, the first NAND latch circuit effects a latch operation on complementary clock signals long in xe2x80x9cHxe2x80x9d period to thereby recover a duty ratio for the complementary input clock signals to about 50%. The second NAND latch circuit operates as an inverter with respect to the complementary clock signals recovered to the duty ratio of about 50% and thereby outputs the complementary clock signals recovered to a duty of 50%. On the other hand, as illustrated in FIG. 14, the first NAND latch circuit effects an inverter operation on complementary clock signals long in xe2x80x9cLxe2x80x9d period to thereby invert the polarity of each input complementary clock signal. The second NAND latch circuit to which the complementary clock signals whose polarities are reversed by the first NAND latch circuit, effects a latch operation on complementary clock signals long in xe2x80x9cHxe2x80x9d period, thereby recovering duty for the complementary clock signals to about 50% in a manner similar to the above. Thus, even if duty is shifted to either a state in which an xe2x80x9cHxe2x80x9d period is long or a state in which an xe2x80x9cLxe2x80x9d period is long, the duty can be recovered to about 50%. Further, duty can be recovered with relative ease according to only levels of input complementary clock signals and logic operations from timings without outputting narrow or thin pulses equivalent to derivative waveforms due to internal small delays.
When NOR gates are used, as illustrated in FIG. 15, the first logic stage may be configured as a first NOR latch circuit (54) wherein the outputs of one NOR gates are respectively mutually feedback-connected to inputs of the other NOR gates, and complementary clock signals having the phase difference of about half cycle are supplied to the other inputs of the respective NOR gates. The second logic stage may be configured as a second latch circuit (55) wherein the outputs of one NOR gates are respectively mutually feedback-connected to inputs of the other NOR gates, and the outputs of the NOR gates of the first latch circuit are respectively supplied to the other inputs of the respective NOR gates. According to the configurations, the NOR latch circuits effect a latch operation on complementary clock signals long in xe2x80x9cLxe2x80x9d period and effect an inverter operation on complementary clock signals long in xe2x80x9cHxe2x80x9d period respectively. The polarities of the clock signals are set in reverse as compared with the NAND latch circuits. However, the duty for the complementary clock signals is recovered to about 50% as a result.
Since the NAND latch circuits or the NOR latch circuits have static latch forms respectively, a duty shift equivalent to a delay corresponding to a gate one-stage takes place. As means for reducing the duty shift to the utmost, inverters whose logic threshold voltages are respectively set high from an intermediate level of a source voltage, may be connected to their corresponding outputs of the second latch circuit (each of second NAND latch circuit and second NOR latch circuit) in the case of the NAND latch circuit. In the case of the NOR latch circuit, inverters whose logic threshold voltages are respectively set low from an intermediate level of a source voltage, may be connected to their corresponding outputs of the second latch circuit. Alternatively, the logic threshold voltages of the NAND gates of the first and second latch circuits (44, 45) may be set low from the intermediate level of the source voltage. Further, the logic threshold voltages of the NOR gates of the first and second latch circuits (54, 55) may be set high from the intermediate level of the source voltage.
The duty shift is developed even in each clock control logic circuit for controlling the selection of go clocks, the stop of the supply thereof, etc. When the duty shift developed therein is also an object to be recovered, the complementary clock signals having the phase difference of about half cycle may be supplied to their corresponding inputs of the first latch circuits (44, 54) through the clock control logic circuits (56A, 56B) respectively. In brief, a duty correction circuit is placed in the vicinity of flip-flops of a logic circuit unit.
[2] A second aspect of the present invention aims to perform the extraction of a short xe2x80x9cHxe2x80x9d period in each of complementary clock signals, or the extraction of a short xe2x80x9cLxe2x80x9d period therein and the reversal thereof, or perform the extraction of a short xe2x80x9cLxe2x80x9d period or the extraction of a short xe2x80x9cHxe2x80x9d period and the reversal thereof in reverse, thereby to achieve the recovery of a duty of about 50%. Namely, a semiconductor integrated circuit has an oscillator circuit which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%, an output converter which converts the complementary cycle signals outputted from the oscillator circuit to predetermined logic levels and outputs complementary clock signals having a phase difference of about half cycle therebetween, and a logic circuit unit which inputs the complementary clock signals outputted from the output converter and performs a logic operation. The logic circuit unit includes a duty correction circuit which corrects a duty shift between the complementary clock signals, which is developed at the output converter, and recovers the same to about 50%. As illustrated in FIG. 27, the duty correction circuit includes a first logic stage (110) which performs a logic operation for determining a duty ratio for the complementary clock signals, maintaining a period for a first logical value so as to be shorter than a duty ratio of about 50% with respect to complementary clock signals having a duty ratio set to be shorter than the period for the first logical value at a duty ratio at which the period for the first logical value is about 50%, and correcting the period for the first logical value so as to be shorter than the duty ratio of about 50% with respect to complementary clock signals having a duty ratio set to be longer than the period for the first logical value at the duty ratio at which the period for the first logical value is about 50%, and a second logic stage (111) which inputs the complementary clock signals outputted from the first logic stage, effects a correction for setting a duty ratio to about 50% thereon and produces an output therefrom.
According to a specific form of the duty correction circuit, a first logic stage includes a first NAND gate (70) which inputs one of complementary clock signals being a phase difference of about half cycle therebetween and an inverted signal of the other thereof, and a second NAND gate (71) which inputs the other of the complementary clock signals being the phase difference of about half cycle therebetween and an inverted signal of the one thereof. A second logic stage includes a first conduction type first transistor (72) switch-controlled by the output of the first NAND gate and connected to a source voltage and an output terminal, and a second conduction type second transistor (73) switch-controlled by an inverted signal of the output of the second NAND gate and connected to a circuit""s ground voltage and the output terminal. A capacitor (74) is connected to the output terminal. The capacitor (74) makes use of only parasitic capacitance, and elements might not demonstratively be laid out on the layout of the semiconductor integrated circuit. However, it is identical in operation to the case where the capacitance is demonstratively provided.
As illustrated in FIG. 30, a NAND latch circuit wherein the output of one NAND gate (78) is mutually feedback-connected to the input of the other NAND gate (79), and the output signals of the first and second NAND gates are respectively supplied to the other inputs of the respective NAND gates, may be adopted as the second logic stage. At this time, the capacitance is not essential.
[3] A semiconductor integrated circuit according to a third aspect of the present invention has an oscillator circuit which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%, an output converter which converts the complementary cycle signals outputted from the oscillator circuit to predetermined logic levels and outputs complementary clock signals having a phase difference of about half cycle therebetween, and a logic circuit unit which inputs the complementary clock signals outputted from the output converter and performs a logic operation. The logic circuit unit includes a duty correction circuit which corrects a duty shift between the complementary clock signals, which is developed at the output converter, and recovers the same to about 50%. The duty correction circuit includes flip-flops (80, 81) which respectively divide complementary clock signals having a phase difference of about half cycle therebetween into two, and a logic gate circuit (82) which receives the outputs of the flip-flops as two inputs, brings the clock signals into status changes each time the two inputs coincide or uncoincide, and outputs the state-changed signals therefrom. The oscillator circuit is a voltage-controlled oscillator of a PLL circuit, for example.
[4] According to the invention grasped on a dominant conception basis, which includes both the first and second aspects, a semiconductor integrated circuit has an oscillator circuit which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%, an output converter which converts the complementary cycle signals outputted from the oscillator circuit to predetermined logic levels and outputs complementary clock signals having a phase difference of about half cycle therebetween, and a logic circuit unit which inputs the complementary clock signals outputted from the output converter and performs a logic operation. The logic circuit unit includes a duty correction circuit which corrects a duty shift between the complementary clock signals, which is developed at the output converter, and recovers the same to about 50%. The duty correction circuit has a first logic stage which inputs the complementary clock signals having passed the output converter, and a second logic stage which inputs the output of the first logic stage. The first logic stage performs a logic operation for determining a duty ratio for the complementary clock signals, correcting complementary clock signals having a duty ratio set to be shorter than a period for a first logical value at a duty ratio at which the period for the first logical value is about 50%, to a duty ratio of about 50% or maintaining the period for the first logical value so as to be shorter than the duty ratio of about 50%, and correcting the period for the first logical value so as to be shorter than the duty ratio of about 50% with respect to complementary clock signals having a duty ratio set to be longer than the period for the first logical value at the duty ratio at which the period for the first logical value is about 50%. The second logic stage inputs complementary clock signals outputted from the first logic stage, brings a duty ratio thereof to about 50% and produces an output therefrom.